The invention relates to computer circuits and, more specifically, to data communications between integrated circuit computer chips.
One major challenge in the design of high-performance computer systems is how to increase the speed with which the data is transferred among parts of the computer and the band width, that is, the number of data bits that can be transmitted in parallel. Particular limitations are faced in the design of computers implemented with very large-scale integrated circuits (VLSI). The number of terminals for outside connections on VLSI chips are severely limited, and space for transmission wiring is at a premium. Furthermore, the so-called Delta-I noise presents a serious obstacle to increasing the data rate and increasing the band width. Delta-I noise takes the form of noise spikes occurring on power supply leads as a result of the switching of binary signal gates between the ON and OFF states defining the opposite states of binary signals. The Delta-I noise tends to be a limiting factor in the transmission of binary data where a large number of binary signals are transmitted in parallel and at a relatively high frequency.
One known approach to minimizing the effect of Delta-I noise is the use of a differential driver circuit which converts one binary signal to two separate signals and transmits the two signals on two separate transmission wires. The value of the data transmitted on the two separate wires is derived at the receiving end by a differential receiver. A serious disadvantage of this approach is that two transmission wires, and therefore two connections to the integrated circuit chip, are needed for each bit of data. Since integrated circuit chips are typically I/O limited, i.e. the useful capacity of this chip is limited by the number of external connections and the use of two terminals for data bit is a serious drawback. Furthermore, this prior art approach minimizes the effect of Delta-I but does not reduce Delta-I noise.